PCB/HDI microvia laser drilling cannot be selected from board thickness or a target hole diameter alone. The real stack of dielectric, copper, glass reinforcement, adhesive, solder mask or coverlay, together with the target layer, hole type, datums, panel warpage, desmear and plating flow, determines whether a CO2, UV or combined route should enter sample validation.
Evidence note: This page is an application and validation framework, not a published customer case or a promise of universal diameter, thickness, speed, yield or “no heat impact.” The final source, settings, cycle time and acceptance criteria require representative boards, controlled drawings, downstream-process inputs and engineering review.
Lock the stackup, target copper and production inputs first
| Input category | Information required | Decision supported |
|---|---|---|
| Stackup and materials | Core or substrate, resin and glass system, copper, adhesive, coverlay or solder mask, and the delivered state of each layer | Candidate wavelength, layer-removal sequence, extraction and downstream boundary |
| Target layer and copper surface | Entry copper, target copper or capture pad, surface preparation, and layers that may or may not be touched | Copper opening, copper stopping, staged processing or a combined route |
| Geometry and datums | Blind via, through hole or window; position, array, entry and bottom geometry, taper requirement, fiducials and artwork files | Scan path, vision registration, distortion compensation and inspection points |
| Production and downstream flow | Panel or web format, warpage and vacuum area, hole count and distribution, batch demand, desmear, plating and electrical test | Fixture, zoned processing, handling, cycle validation and traceability scope |
How to screen CO2, UV and combined routes
| Candidate route | Tasks to validate first | Risks that must be checked |
|---|---|---|
| CO2 | Micro-blind vias in resin, glass-reinforced dielectric and organic insulation for HDI boards, package substrates and multilayer PCBs | Dielectric residue, exposed glass, carbonization, taper, target-copper condition and batch throughput |
| UV | Fine holes and windows in FPC, rigid-flex boards, fine-line circuits, coverlay, adhesive and electronic functional films | Selectivity between copper and dielectric, edge and heat impact, redeposition, registration, warpage compensation and area consistency |
| Combined or staged route | Stackups in which one source cannot satisfy entry-layer, dielectric-removal, target-copper-protection and throughput criteria together | Inter-step registration, work-in-process handling, cleaning, cumulative error, data binding and total cost |
The current equipment pages describe configurable CO2 PCB dielectric laser drilling and PCB/FPC UV microvia drilling platforms. They are candidate routes, not substitutes for physical-sample comparison.
Define each hole type in measurable terms
- Micro-blind via: Define the entry, target copper, design depth, usable bottom area, allowed taper and desmear boundary.
- Through hole: Define the penetrated layers, entry and exit condition, back-side protection, burr or residue criteria and downstream metallization.
- Window and selective-layer removal: Separate coverlay, adhesive, solder-mask and copper-exposure tasks instead of assuming that different material responses share one recipe.
- Array and panel datum: Record position, pitch, zones, fiducials, panel orientation, warpage and vacuum state so within-panel and panel-to-panel consistency can be evaluated.
Hole-quality metrics and inspection methods
| Quality object | Suggested record | Validation method |
|---|---|---|
| Geometry and registration | Entry and bottom dimensions, roundness or profile, taper, position and array consistency | Calibrated optical or microscope measurement sampled by panel zone and datum position |
| Wall and residue | Resin residue, exposed glass, debris, carbonization, redeposition and rim condition | Surface microscopy and cross-section inspection of representative samples when required by the acceptance plan |
| Target copper and adjacent layers | Bottom-copper exposure, pitting or damage, surface contamination, and impact on nearby traces or dielectric | Microscopy and cross-section review, supplemented when required by cleaning, plating and electrical validation |
| Batch consistency | Changes in dimension, residue and position across zones, panels, lots and continuous runs | A fixed sampling plan with first-piece and continuous-batch checks linked to recipe, material lot and inspection records |
Results after drilling, after desmear and after plating should be recorded as separate stages; a downstream result should not replace evaluation of the laser-drilling step. Review the adjacent polymer and copper material boundaries.
Recommended sample DOE and acceptance flow
- Freeze the inputs: Use representative boards and controlled drawings to confirm the stack, target layer, delivered state, hole type, datums, downstream flow and inspection method.
- Screen by group: Compare CO2, UV or staged candidates on the same material lot. Organize variables around layer response and quality risk instead of assuming a universal parameter window.
- Inspect critical locations: Cover panel center and edge, processing zones, entry and bottom, dense arrays and stitching boundaries; record geometry, residue, copper condition and heat impact.
- Connect downstream steps: Apply the project-defined cleaning, desmear, plating or electrical tests while preserving the result and responsibility boundary for each stage.
- Verify repeatability: Repeat with the intended fixture, vision, vacuum, extraction and continuous-run conditions, then freeze equipment, recipes, permissions and traceability fields only after agreed criteria are met.
Use the laser drilling process, laser micromachining process and FPC UV processing validation pages to separate adjacent application boundaries.
Evaluate throughput, automation and TCO by qualified panels
- Cycle time: Include vision registration, focus or height compensation, zoned scanning, flipping, handling, extraction and inspection rather than comparing only beam-on time per hole.
- Output: Compare qualified panels or accepted batches after the agreed inspection and downstream flow; rework, scrap and repeat inspection change real capacity.
- TCO: Record source and optics, fixtures, automation, extraction and filters, maintenance, consumables, metrology, downtime, training, data interfaces and extra work-in-process handling for a combined route.
- Scale-up risk: After sample approval, repeat with the target panel format, hole distribution and continuous-run conditions to check area consistency, material-lot change and maintenance intervals.
Application page versus equipment pages
This application page owns PCB/HDI stackup, CO2-versus-UV route selection, hole types, quality metrics, inspection, DOE, throughput and TCO decisions. The laser drilling systems collection and equipment pages own configurable source, scanning, vision, motion, fixturing, extraction, automation and data interfaces. Equipment or concept images are not evidence of hole quality, and this page is not an unauthorized customer case.
Next step
Confirm the task boundary in Consumer Electronics Laser Solutions. When the stackup, target copper, panel and via artwork, delivered state, downstream flow, inspection method, batch demand and target cycle time are ready, continue to Sample Testing & Process Validation or submit the PCB/HDI boards, drawings and acceptance criteria.